1. Field of the Invention
The present invention relates to a memory device that performs data transfer with a host apparatus and, more particularly, to a memory device including a nonvolatile semiconductor memory.
2. Description of the Related Art
Presently, memory cards including nonvolatile semiconductor memories are used as memory devices for recording music data, video data, and the like. In the nonvolatile semiconductor memories, data does not disappear even when the power supply is turned off, and can also be rewritten (updated). A NAND flash memory and the like are used as the nonvolatile semiconductor memories.
In the NAND flash memory, data is written for each page (e.g., 2, 4, or 8 Kbytes), and erased for each block (e.g., 512 Kbytes or 1 Mbytes) composed of a plurality of pages. Also, data write to the NAND flash memory has the following limitations.
(1) Data must be erased for each block beforehand.
(2) When writing data in the same block, data to be written next to preceding data must be written at an address larger than that of the preceding data.
For example, when writing new data in a block in which data is already written, an erased block is separately prepared, and the new data is written in this erased block. In addition, data is copied from the original block to a portion except for the portion where the new data is written. That is, data write like this is implemented by a so-called “moving” process. Especially when data write occurs from a host apparatus at random logical addresses, this moving process frequently occurs to deteriorate the write performance.
In the recent NAND flash memories, the block size is increasing as the capacity increases. As the block size increases, the inter-block data copying time prolongs, and a maximum value of the moving time increases. This prolongs the write time (also called the busy time) in a memory card with respect to data write at random logical addresses.
On the other hand, if a data write process specialized to shorten the time of data write at random logical addresses is used in order to shorten the busy time, the speed of data write at sequential logical addresses decreases.
As a related technique of this kind, a technique that presumes the performance of a memory device is disclosed (Jpn. Pat. Appln. KOKAI Publication No. 2006-178923).